A common form of analog to digital converter system [ADC system] uses an array of proportionately sized capacitors which are controlled by sequential approximation register logic [SAR logic]. In this variety of ADC system, a comparator is used to perform sequential comparisons of the input voltage to a threshold voltage associated with the comparator. Accordingly, the accuracy of the comparator in the system is vital to the accurate conversion of the analog signal to a representative digital value. Because of the design of conventional comparator circuits, hysteresis in the threshold voltage of the MOSFETs within the comparator can cause comparison errors when high voltages are placed on the inputs of the comparators. This hysteresis problem is a practical limitation when trying to implement high resolution ADC systems when the voltage shift resulting from the hysteresis becomes large when compared to the voltage step associated with the least significant bit position of the digital value output by the ADC system.
Accordingly, a need has arisen for a high resolution ADC system which converts an analog signal into a digital value but which allows for the effect of the hysteresis in the threshold voltage of the MOSFETs comprising the comparators used in the ADC system.